Jump
Type Instruction Format
There are
three types of instruction format which is Register Type, Immediate Type and
Jump Type. However this post will only talk about Jump Type, also known as the
J-Type.
J-Type
consist of two direct jump instructions : “j” and “jal”. These instruction will
require a memory address to specify their operand. J-type instruction use an
opcodes of 00001x.
J-type format
is as follow :
Addressing Modes
There are
five types of addressing modes. There are : Register addressing, Immediate
addressing, PC-relative addressing, Base addressing and Psedo-direct
addressing. Here we will only explain the last three types.
PC-Relative
Addressing
PC-relative
addressing is usually used in conditional branches. PC refers to special
purpose register, Program Counter that stores the address of next instruction
to be fetched.
In
PC-relative addressing, the offset value can be an immediate value or an interpreted
label value. The effective address is the sum of the Program Counter and offset
value in the instruction. The effective address determines the branch target.
PC-relative
addressing implements position-independent codes. Only a small offset is adequate
for shorter loops.
For
example, instruction beqz
$t0, strEnd
Where;
$t0=rs
100=offset
Thus;
if ($t1==0) goto PC + 4 + (4*2)
In this
instruction, beqz is a conditional instruction that branches to label in the
code if the content of $t0 is equal to zero. If the current address for branch
instruction in execution is 0x4000000C, the effective address will be 40000018.
The details of the example will be shown in the following tables.
Address
|
Instruction
|
Note
|
40000008
|
subi
$t0,$t0,1
|
Binary code to beqz
$t0, strEnd is 0x110000004, which means 2 instructions from the next instructions.
PC=0x4000000C
PC+4=0x40000010
Add 4*2=0x00000008
Effective
Address=0x40000018
|
4000000C
|
beqz
$t0,label
|
|
40000010
|
subi
$t0,$t0,1
|
|
40000014
|
subi
$t0,$t0,1
|
|
40000018
|
strEnd:
subi
$t0,$t0,1
|
|
4000001C
|
subi
$t0,$t0,1
|
Base
Addressing
Is also
known as indirect addressing, where a register act as a pointer to an operand
located at the memory location whose address is in the register.
The
register is called base that may point to a structure or some other collection
of date and immediate value is loaded at a constant offset from the beginning
of the structure. The offset specifies how far the location of the operand data
from the memory location pointed by the base.
The address
of the operand is the sum of the offset value and the base value(rs). However,
the size of the operand is limited to 16 bits because each MIPS instructions
fits into a word.
The offset
value is a signed number which is represented in a two’s complement format.
Therefore, offset value can also be a negative value.
Consider
the following instruction:
lw $t1,
4($t2)
where $t1=rs
$t2=base(memory address)
4=offset value
Thus; $t1=
Memory [$t2+4]
The instruction
will load register $t1 with the contents of the memory location four words
onward from the location pointed by register $t2.
If the
offset is negative value; i.e. -4, the operand data is located by 4 bytes back
from the location pointed by register $t2.
lw $t1,
-4($t2)
$t1= Memory
[$t2-4]
Pseudo-Direct
Addressing
Pseudo-direct
addressing is specifically used for J-type instructions, “j” and “jal”. The
instruction format is 6 bits of opcode and 26 bits for the immediate value(target).
In
Pseudo-Direct addressing, the effective address is calculated by taking the
upper 4 bits of the Program Counter(PC), concatenated to the 26 bit immediate
value, and the lower two bits are 00.
Therefore,
the new effective address will always be word-aligned
and we can never have a target address of a jump instruction with the two bits
anything other than 0 0 and creates a complete 32-bits address. Since the upper
4 bits of the PC are used, this constrains the jump target to anywhere within
the current 256 MB block of code(1/16 of the total 4GB address space). To jump
anywhere within the 4GB space, the R-type instructions “jr” and “jalr” are
used, where the complete 32-bit target address is specified in a register.
NOTE:
word-aligned : This means that an address(
unless you use one of the special instructions for loading or storing bytes)
must be a multiple of four. An address that isn’t a multiple of four can lead
to undesirable results.
Consider
the following instruction:
j label
The
implementation of the instruction is best described using the following
operation:
Yap Chi Hian B031210334
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