MIPS Simulator ( Memory allocation, Data alignment, Register )

Memory Allocation

MIPS processors typically divide memory into three part which are text segment, data segment, and stack segment.

1.      Text segment

This segment is handle machine language code for instruction in source program file.

2.      Data segment

This segment is handle the data on the program operate it. It will separate in two parts to process. First part is static data which are contain data that are statically allocated whose size and when program access, them will not change. Dynamic data is another top of static data. This data in program excute will allocated and deallocated.

3.      Stack segment

This segment will help to resides the user address space. When it is in the high level language program, the local variables and parameters will pop and push on the stock for expand operating system and shrink the stock segment to the data segment. It also consider a step to change language before enter the data segment part.

     

	Stack segment
Dynamic data
Static data	Data segment
	Text segment
Reserved

                                      

     Memory Layout

Data Alignment

Data Type	Size (Binary)	Size (Hexadecimal)
Byte	8 bits	2 bits
	Ex: 11111111	Ex: FF
Word	4 bytes, 32 bits	1 byte, 8 bits
Double Word	8 bytes, 64 bits	16 bits

                                                Data Sizes

			Double Word
	Word				Word
Half Word		Half Word		Half Word		Half Word
Byte	Byte	Byte	Byte	Byte	Byte	Byte	Byte

                                                    Data Alignment

Register

-          MIPS contain 32 register that are numbered as from 0 to 31.

Register Name  ( Mnemonic Name )	Register Number	Usage
$zero	$0	Constant with value 0
$at	$1	Assembler Temporary (For reserved, no used by user program or compiler)
$v0 - $v1	$2 - $3	Expression evaluation and result of a subroutine (used to return value from function)
$a0 - $a3	$4 - $7	Argument to a subroutine (used to pass by first four arguments to routine)
$t0 -$t7	$8 - $15	Temporary (As caller - saved registers for hold a temporary values, no preserved in function call)
$s0 - $s7	$16 - $23	Saved temporary (As callee - saved register for hold long-lived value, preserved infunction call)
$t8 - $t9	$24 - $25	More temporary to used
$gp	$28	Global pointer (Points in middle of a 64K block of memory,static data segment, preserved on call)
$sp	$29	Stack pointer (Points fo last location on stack, preserved on call)
$fp	$30	Frame pointer (preserved on call)
$ra	$31	Return address (Use jal instruction)
$k0 - $k1	$26 - $27	Operating system (For reserved, no used by user program or compiler)

                               MIPS Register Convention

-          Besides that, Coprocessor 0 is contains exception control register for purpose in exceptions. SPIM does no implement all coprocessor 0’s register because they are not much useful or affected in a simulator or part of memory system. However, it also provide a trap registers to helping in coprocessor.

Register Name	Register Number	Usage
BadVAddr	8	Memory address at which address exception occurred
Status	12	Interrupt mask and enable
Cause	13	Exception type and pending interrupt bits
EPC	14	Address of intstruction that caused exception

-          These register is one of the part coprocessor 0’s register set accessed by instruction of mfc0 and mtc0.

                        15                             8                                 4                        1     0

Interrupt Mask

UM

EL

IE

                                                Status Register

-          Bits of status register that are implement by SPIM. Interrupt mask will hold a bit for each after 8 interrupt level. If just have a bit, interrupt is able to function it. However, if there is zero bit, interrupt is no allowed. The user mode (UM) bit is 0 mean the program is run in kernel mode and UM is 1 bit mean the program is go on user mode. The exception level (EL) commonly is on 0 and only will change to 1 when exception running. Interrupt Enable (IE) is 1 bit, interrupt level is allow and when it is 0, interrupt is no allowed.

31                              15                                  8                          6                           2

BD

Pending Interrupt

Exception Code

                                                Cause Register

-          The eight bit in pending interrupt mean it has 8 interrupt level. A bit becomes 1, it is showing an interrupt is process but has no services. However a bit becomes 0, it is showing no interrupt allow. The exception code bits are contain a list of code.

Number	Name	Cause of exception
0	int	Interrupt (for hardware)
4	AdEL	Address error exception ( for load address and instruction fetch the address)
5	AdES	Address error exception ( for  store address)
6	IBE	Bus error on instruction fetch
7	DBUS	Bus error on data load and store
8	SYSCALL	Syscall the exception
9	BKPT	Breakpoint exception
10	RI	Reserved instruction exception
12	OVF	Arithmetic overflow exception
13	Tr	Trap

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