I - Type Instruction Format and Addressing ( MIPS )

Immediate Type ( I – Type )

I – type instruction format is includes with an immediate operand, branch instructions, and load & store instructions. Immediate type is to converted into machine code words . All memory in the MIPS accesses are handle by the main processor. So co – process of load and store also include in this category. All opcodes are used for I – type instruction except 000000, 00001x, and 0100xx.

Basic instruction format

op	rs	rt	Immediate
Operation code	Source register specifier	Target register specifier or branch condition	Immediate, branch displacement or address displacement

Instruction coding

-          immediate from 0^th bit to 15^th bit ( 16 bits )

-          rt from 16^th bit to 20^th bit ( 5 bits )

-          rs from 21^th bit to 25^th bit ( 5 bits )

-          op from 26^th bit to 31^th bit ( 6 bits )

Immediate type application

a.       Immediate

ALU Usage – addi  rt,  rs,  imm

1.      PC update: No any update beyond this normal increment.

2.      Source operand fetch: There are two source operands which are rs and immediate field. For all instructions except sltiu the immediate field is a sign extended and it is a zero extended. Sltiu instruction is not considered in the theory Patterson and Hennessey.

3.      ALU operation: The opcode will determined the ALU operation.

4.      None any memory access required.

5.      The register result from ALU will written in rt.

b.      Branch

ALU Usage – beq  $rs,  $rt,  imm

1.      PC update: If the branch condition is true then PC <-- PC + 4 + ( sign- extended immediate field ) <<2.

2.      Source operand fetch: There are two source operands which are rs and rt.

3.      ALU operation: The source operands are subtracted for purpose comparison.

4.      None any memory access required.

5.      None register write for the result.

c.       Load

ALU Usage – lw  rt,  imm(rs)

1.      PC update: No any update for this normal increment.

2.      Source operand fetch: There are two source operands which are rs and the sign extended immediate field.

3.       ALU operation: Two source operands are added for getting the memory access.

4.      A memory read control signal will send it to memory. Therefore the memory address will receive the result from the ALU.

5.      The register data from the memory will written in rt.

d.      Store

ALU Usage – sw  rt,  imm ( rs )

1.      PC update: No any update for this normal increment.

2.      Source operand fetch: There are two source operands which are rs and the sign extended immediate field. The rt register is as fetched.

3.      ALU operation: The two source operands are added to get the memory address.

4.      Sign write control of memory is sent to memory, Memory address will receive the result from the ALU. The write data of memory address will receive from the contents of rt.
5.      None register written.

e.       Register Jump

ALU Usage – beq  $rs,  $rt,  imm

1.      PC update: jr and jalr :  PC <--   rs

2.      Source operand fetch: There just have one source operand that is used is rs register.

3.      None ALU operation involved.

4.      None any memory access require.

5.      Register write:

jr:               There is no register write

jalr:            rd <-- PC + 4

For jarl, the incremented PC value will get before the target address which is places into PC. There will more easy to do when getting with the edge – triggered clocking. There is adder to produce the PC + 4 values. PC will not change until next cycle and adder for output also will not change until next cycle.

f.       Non – Register Jump

ALU Usage – jal  target

1.      PC update:

jr  and  jalr :                       PC <--  target address

The target address is the concatenation of the high order 4 bits of PC + 4, target field of the instruction, and two 0 bits.

2.      None source operands fetch, ALU operation and memory access involved.

3.      Register write:

jr :                                      No register write

jal :                                    ra  <--  PC + 4

For jal, the incremented PC value must recorded before the target address store into PC.When with the edge – triggered clocking will easy to do. The PC and adder output will no change until the start of next cycle.

Immediate Addressing

It is an addressing form in which the byte value embedded in the instruction is the actual operand. It  is located immediately after the opcode for the instruction itself.  In immediate addressing, the operand will consists a constant within the encoded instruction. Immediate addressing almost similar with the register addressing because the instruction will be executed faster without involve in memory access. However, the size of operand is limit to 16 bits only. The jump instruction format also under the immediate addressing, where the destination is held in the instruction.One of the characteristics of immediate instruction, the name of operand have i at the end such ori, addi...

Example instruction:

            addi   $t1, $t0,  12

Where $t1 = rs;

            $t0 = rt;

            12 = immediate value              Therefore: $t1 = $t0 + $12

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